Serializer/deserializer (“SERDES”) devices are frequently used in high-speed communication networks in which an interface must be provided between parallel bus-connected devices and high-speed serial communication networks, such as those implemented through optical fiber interconnections. Current SERDES devices utilize Voltage Controlled Delay Locked Loops (“VCDLs”) to frequency and phase lock to an incoming serial data stream. Currently, SERDES devices are testing using either built-in self test (“BIST”) modes or through board connections to external test equipment, such as automated test equipment (“ATE”).
For both types of testing situations, the receive functionality of the SERDES device cannot be fully tested because the incoming serial data, generated by the SERDES device itself or through the external test equipment, is synchronous to the reference clock utilized in the VCDL. At the same time, there is no asynchronous clock available for testing using external test equipment (e.g., ATEs) or in BIST modes. As a consequence, in the prior art, the receive functionality of SERDES devices is only tested for frequency and phase locking to synchronous serial data, for both external test and BIST modes.
Such current testing modes are, as a consequence, insufficient. Such synchronous testing does not adequately test SERDES devices, particularly those having VCDL or other delay locked loops (“DLLs”), because not all possible delay combinations are tested. The SERDES devices are not tested fully to determine whether the devices accurately lock to asynchronous incoming data, for both frequency and phase.
Accordingly, a need arises for an apparatus, system and method that easily and efficiently permit asynchronous testing SERDES devices. Such testing should determine whether the devices accurately lock to asynchronous incoming data, for both frequency and phase, for all delay combinations.